SRAM memories in advanced technology nodes consume significant amount of leakage power. Powering down memories when not in use for long periods is one of the methods used to reduce overall power consumption in a system on a chip (SOC). The memories will be powered up when the system requires the memories to be accessed. Before accessing a powered down memory, a wakeup request must be sent to power up the memory. The access cannot be made until the memory is completely powered up. This is conventionally accomplished by delaying the actual access in software for a predefined time or till the completion of wakeup is signaled through some means such as an interrupt or polling a status register. In cases where the software does not directly control access to the memories, such as a cache miss, the software must not make any access that will result in an access to powered down memory. Thus additional software overhead or limitations are incurred in accessing a powered down memory.